There is no bundle for Verilog HDL, but it has a lot in common with C and Pascal, so I duplicated the C language and have been hacking on that to get the syntax coloration mostly working. I've run into a bit of trouble with the constant expression syntax though. In Verilog constants have this form: 8'b00100011 (8 bit binary) 6'o35 (6 bit octal) 12'h3A2 (12 bit hex)
The initial number is optional, so 'b10110 would be a 5 bit binary constant. In addition to numbers, z and ? can also appear sometimes to indicate high impedance or indeterminate values. I've tried the following syntax for the binary constants:
...|([0-9]*)'b[0-1zZ?]*)|...
When I hit the test button it highlights everything from the b on. I'm guessing it is not able to escape the single quote. I've also tried escaping the b as well and it didn't make any difference. Is there a way around this? Is there somewhere I can find the detailed syntax rules for the matching expressions and bundles in general? I did a quick look through the WIKI and didn't see anything obvious.