[SVN] r10828 (VHDL)

Brian Padalino bpadalino at gmail.com
Tue Nov 18 22:47:25 UTC 2008


Made it a word boundary instead of whitespace surrounding (?i:is|port) in component_pattern.

Changed:
U   trunk/Review/Bundles/VHDL.tmbundle/Syntaxes/VHDL.tmLanguage



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